CPC700 memory controller and pci bridge high-performance companion chip for powerpc 60x and 7xx processors overview the CPC700 tm memory controller and pci bridge brings high-performance, real-time control to powerpc 60x/7xx driven designs. this single-chip micro- processor companion is specifically designed for embedded systems to provide a general purpose bridge to any pci bus. the CPC700 companion chip also includes a high-speed memory controller, internal peripherals, and control for external rom and external peripherals. this CPC700 companion chip can function as a host bridge, as the basis for an intelligent add-in pci controller, or in stand-alone modes. this versatility and the following features can help lower costs, enhance board efficiency and reduce your time-to-market. ? powerpc 60x/7xx interface (66 mhz) ? 66 mhz sdram interface ? external peripheral bus ? pci 2.1 compliant interface (32-bit, 25 to 66 mhz) ? supports internal or external pci bus arbitration ? interrupt controller ? programmable timers ? two full-duplex uarts (16550) ? two i 2 c interfaces ? byte swapping options ease communication in little-endian systems ? jtag for board-level testing general ? extensive programmability ? flexible and programmable error handling processor interface the powerpc tm processor bus interface includes the interface to the system memory controller, as well as the processor local bus (plb) master/slave interface. ? 1 level processor address pipelining ? processor bus arbiter ? l1 cache coherency support ? two 32-byte write buffers ? provides error tracking/status ? lwarx/stwx support (reservation cancel- ling snoops) ? supports address only cycle memory controller this memory controller provides the local powerpc processor with a low- latency access path supporting external peripherals and 5 banks of local memory. sdram ? up to 4 banks ? 11x9 to 13x11 addressing (for 2 and 4 internal bank sdrams) ? 8 mb to 512 mb per bank CPC700 block diagram uart uart timers i c 2 jtag interrupt controller processor interface pci interface memory controller (sdram, rom, peripherals) 66 mhz processor local bus (plb) 33 mh on-chip peripheral bus (opb) z i c 2 32 or 64-bi t 13-bi t data/address control 32-bi t 64-bi t control data addr. control data addr. 64-bi t 32-bi t data addr. 32-bi t 32-bi t ecc 8-bi t opb bridge
*07gk21026700* g gk21-0267-00 ? programmable timings and address mapping ? cas before ras refresh ? ecc support across data and address ? supports hardware coherency relative to pci access of local memory ? page mode accesses ? 66 mhz memory bus frequency ? 72-bit memory interface with ecc ? self-refresh mode support r o m/ex t e r na l p e r i p he r a l ? supports rom, flash rom, sram, and peripherals ? burst and non-burst devices ? 1-5 banks (shared with sdram) ? 8-, 16-, 32-, and 64-bit data bus widths ? programmable timing and address mapping ? shared address/data/control with sdram interface ? external latch control for shared address bus support ? peripheral device pacing with external ready pci interface ? pci 2.1 compliant ? 32-bit pci address/data bus ? supports 25 to 66 mhz pci bus speeds ? supports processor access to all pci address spaces ? error tracking/status ? support for synchronous and asynchro- nous clocking ? internal pci arbitration ? support for fair external arbitration interrupt controller ? supports twelve (12) external interrupts ? option for prioritized interrupt handler vector generation uart (2) ? compatible with the ns 16550 ? 16-byte send fifo, 16-byte receive fifo ? programmable baud rate generator ? supports 5- to 8-bit word si ze, 1 or 2 stop bits, even/odd/no parity i 2 c (2) ? 100 and 400 khz operation ? 8-bit data transfers ? 7- and 10-bit address decode/generation ? master/slave capability general purpose timers ? 32-bit time base, based on system clock ? five capture event timers ? five compare timers jtag ieee 1149.1 (jtag) boundary scan is included to facilitate board level testing ? international business machines corporation 1998 all rights reserved printed in the united states of america 7-98 CPC700, ibm, ibm logo, and powerpc are trademarks of international business machines corporation in the united states and/or other countries. other company, product, and service names may be trademarks or service marks of others. the information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibms product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all the information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environ- ments may vary. the information contained in this document is provided on an ?as is? basis. in no event will ibm be liable for any damages a r i s i n g d i r e c t l y o r i n d i r e c t l y f r o m a n y u s e o f t h e i n f o r m a t i o n c o n t a i n e d i n t h i s d o c u m e n t . ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at: http://www.ibm.com the ibm microelectronics division home page can be found at: http://www.chips.ibm.com CPC700 companion chip specifications technology 0.35m (0.27m l eff ) cmos power supply 3.3v +/- 5% temperature range -40c to 105c packaging 474-pin cbga
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